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Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Solving for R 1 :
R 1 [k ? ] =
R F [k ? ] × 4 × ESR[m ? ] × V FB [V]
2 π × f CO [kHz] × L[ μ H] × V OUT_ [V]
R I
V OUT_
R 1
C CF
R F
C F
where V FB is the 0.6V (typ) FB_ input-voltage set-point,
L is the value of the regulator inductor, ESR is the
C I
FB_
series resistance of the output capacitor, and V OUT_ is
the desired output voltage.
R 2
V REF
COMP_
1) C F is determined from the compensator’s leading
zero, f Z1 , and R F as follows:
C F [ μ F] =
1
2 π × R F [k ? ] × f Z1 [kHz]
Figure 6a. Type III Compensation Network
GAIN
(dB)
2) C CF is determined from the compensator’s high-fre-
quency pole, f P1 , and R F as follows:
1ST ASYMPTOTE
( )
C CF [ μ F] =
1
2 π × R F [k ? ] × f P1 [kHz]
( ω R I C F ) -1
4TH ASYMPTOTE
R F
R I
( )
3) Calculate R 2 using the following equation:
2ND ASYMPTOTE
R F -1
R 1
3RD ASYMPTOTE
( ω R F C I ) -1
5TH ASYMPTOTE
(R I C CF ) -1
R 2 [k ? ] = R 1 [k ? ] ×
V FB [V]
V OUT_ [V] ? V FB [V]
where V FB = 0.6V (typ) and V OUT_ is the output voltage
of the regulator.
1ST POLE
(AT ORIGIN)
1ST ZERO 2ND POLE
(R F C F ) -1 (R I C I ) -1
2ND ZERO
(R 1 C I ) -1
3RD POLE
(R F C CF ) -1
ω (rad/sec)
Type III: Compensation when f CO < f ESR
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors (MLCCs) are used, the ESR zero fre-
quency (f ESR ) is usually much higher than the desired
crossover frequency (f CO ). In this case, a Type III com-
pensation network is recommended (see Figure 6a).
As shown in Figure 6b, the Type III compensation net-
Figure 6b. Type III Compensation Network Response
f P1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors.
f P1 = at the origin (0Hz)
Depending on the location of the ESR zero (f ESR ), f P2
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple.
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
f P2 =
1
2 π × R I × C I
at the following frequencies:
f P3 attenuates the high-frequency output ripple.
f Z1 =
f Z2 =
f P3 =
2 π × R F × F CF
1
2 π × R F × C F
1
2 π × C I × (R 1 + R I )
1
2 π × R F × ( C F C CF
Since C CF << C F then:
)
=
1
C × C
C F + C CF
Two midband zeros (f Z1 and f Z2 ) are designed to com-
pensate for the pair of complex poles introduced by the
LC filter.
f P3 =
1
2 π × R F × C CF
20
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